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FPGA Prototype of Flexible Heterogeneous multi-ASIP NoC-based Unified Turbo R...
International audience -
Architecture Efficiency of Application-Specific Processors: a 170Mbit/s 0.644mm...
International audience -
FPGA Prototyping and Performance Evaluation of Multi-standard Turbo/LDPC Enco...
International audience -
Compression of redundancy free trellis stages in Turbo-Decoder
International audience -
Parameterized area-efficient multi-standard turbo decoder
International audience -
Analysis of the Convergence Process by EXIT Charts for Parallel Implementatio...
International audience
