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Hardware architectures for successive cancellation decoding of polar codes
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Hardware architectures for morphological filters with large structuring elements
This thesis is focused on implementation of fundamental morphological filters in the dedicated hardware. The main objective of this thesis is to provide a programmable... -
Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip
International audience -
Hardware architecture of Self-Organizing Maps
International audience -
Partial sums generation architecture for successive cancellation decoding of ...
International audience
