Electrical properties and modeling of Advanced MOS devices : FD-SOI Tri-gate device, Junctionless Transistor, and Amorphous-Oxide-Semiconductor Thin Film Transistor
type: Dataset
contact point: Organization
  fn: CCSD
keyword: spiotherengineering-sciences-physicsother
keyword: extraction-de-parametres-electriques
keyword: nano-dispositifs
keyword: infoeu-reposemanticsdoctoralthesis
keyword: proprietes-de-surface-et-interface
keyword: caracterisation-electrique
keyword: surfaceinterface-properties
keyword: techniques-de-mesure-electrique
keyword: nano-device
keyword: electrical-characterization
keyword: electrical-parameter-extraction
keyword: electrical-measurement-techniques
keyword: theses
landing page: https://theses.hal.science/tel-00954637
description: Novel advanced metal-oxide semiconductor (MOS) devices such as fully-depleted-silicon-on-insulator (FD-SOI) Tri-gate transistor, junctionless transistor, and amorphous-oxide-semiconductor thin film transistor were developed for continuing down-scaling trend and extending the functionality of CMOS technology, for example, the transparency and the flexibility. In this dissertation, the electrical characteristics and modeling of these advanced MOS devices are presented and they are analyzed. The sidewall mobility trends with temperature in multi-channel tri-gate MOSFET showed that the sidewall conduction is dominantly governed by surface roughness scattering. The degree of surface roughness scattering was evaluated with modified mobility degradation factor. With these extracted parameters, it was noted that the effect of surface roughness scattering can be higher in inversion-mode nanowire-like transistor than that of FinFET. The series resistance of multi-channel tri-gate MOSFET was also compared to planar device having same channel length and channel width of multi-channel device. The higher series resistance was observed in multi-channel tri-gate MOSFET. It was identified, through low temperature measurement and 2-D numerical simulation, that it could be attributed to the variation of doping concentration in the source/drain extension region in the device. The impact of channel width on back biasing effect in n-type tri-gate MOSFET on SOI material was also investigated. The suppressed back bias effects was shown in narrow device (Wtop_eff = 20 nm) due to higher control of front gate on overall channel, compared to the planar device (Wtop_eff = 170 nm). The variation of effective mobility in both devices was analyzed with different channel interface of the front channel and the back channel. In addition, 2-D numerical simulation of the the gate-to-channel capacitance and the effective mobility successfully reconstructed the experimental observation. The model for the…
identifier: NNT: 2013GRENT075
issued: 2026-05-06T04:11:18.617693
language: fr
modified: 2026-05-06T04:11:18.617697

Electrical properties and modeling of Advanced MOS devices : FD-SOI Tri-gate device, Junctionless Transistor, and Amorphous-Oxide-Semiconductor Thin Film Transistor
type: Distribution
access URL: https://theses.hal.science/tel-00954637
format: HTML
issued: 2026-05-06T04:11:18.628376
modified: 2026-05-06T04:11:18.605169

test_moissonnage_selune
type: Agent