Aging and IC timing estimation at high level : methodology and simulation
type: Distribution
access URL: https://theses.hal.science/tel-00952867
format: HTML
issued: 2026-05-06T05:22:00.539589
modified: 2026-05-06T05:22:00.497816

Aging and IC timing estimation at high level : methodology and simulation
type: Dataset
contact point: Organization
  fn: CCSD
keyword: injection-de-porteurs-chauds-hci
keyword: mpsoc
keyword: marges-temporelles
keyword: slack-time
keyword: hot-carrier-injection-hci
keyword: theses
keyword: physcondcm-genphysics-physicscondensed-matter-cond-matother-cond-matother
keyword: simulation-fonctionnelle
keyword: infoeu-reposemanticsdoctoralthesis
keyword: negative-bias-temperature-instability-nbti
keyword: vieillissement
keyword: conception
keyword: aging
keyword: functional-simulation
landing page: https://theses.hal.science/tel-00952867
description: Nowadays, more and more performance is expected from digital circuits. What’s more, the market requires fast conception methods, in order to propose the newest technology available. Fast conception methods and the utilization of MPSoC have enabled high performance and short time-to-market while taking little attention to aging. However, MPSoC are more and more prone to hardware failures that occur in transistors. Today, the prevailing failure mechanisms in MPSoC are HCI and NBTI. Margins are usually added on new products to avoid failures during execution, by considering worst case scenario for each mechanism. For the newest technology, margins are becoming more and more important and products performance is getting lower and lower. That’s why the conception needs to take into account hardware failures according to the execution of software. This thesis propose a new methodology to simulate aging at high level of abstraction, which can be applied to MPSoC. The method can be applied during product conception, between the specification phase and the production. An empirical model is used to estimate slack time at circuit's end of life. A use case is conducted on an embedded processor and degradation results are reported for a set of applications. The solution enables architecture exploration and MPSoC aging can thus be compared. The software with most severe impact on aging can also be determined.
identifier: NNT: 2013BOR14968
issued: 2026-05-06T05:22:00.513097
language: fr
modified: 2026-05-06T05:22:00.513101

test_moissonnage_selune
type: Agent