ASIC Design Methodologies for 3D NOC Based 3D Heterogeneous Multiprocessor on Chip
type: Dataset
description: In this thesis, we study the exploration 3D NoC architectures through physical design implementations using real 3D technology used in the industry. Based on the proposed 3D design flow focusing on timing verification by leveraging the benefit of negligible delay of microbumps structure for vertical connections, we have conducted partitioning techniques for 3D NoC-based MPSoC architecture including homogeneous and heterogeneous stacking using Tezzaron 3D IC technlogy. Design and implementation trade-off in both partitioning methods is investigated to have better insight about 3D architecture so that it can be exploited for optimal performance. Using homogeneous 3D stacking approach, NoC architectures are explored to identify the best topology between 2D and 3D topology for 3D MPSoC implementation. The architectural explorations have also considered different process technologies highlighting the wire delay effect to the 3D architecture performance especially for interconnect-dominated design. Additionally, we performed heterogeneous 3D stacking of NoC-based MPSoC implementation with GALS style approach and presented several physical designs related analyses regarding 3D MPSoC design and implementation using 2D EDA tools. Finally we conducted an exploration of 2D EDA tool on different 3D architecture to evaluate the impact of 2D EDA tools on the 3D architecture performance. Since there is no commercialize 3D design tool until now, the experiment is important on the basis that designing 3D architecture using 2D EDA tools does not have a strong and direct impact to the 3D architecture performance mainly because the tools is dedicated for 2D architecture design.
identifier: NNT: 2013GRENT006
issued: 2026-05-07T07:31:07.486391
language: fr
modified: 2026-05-07T07:31:07.486395
contact point: Organization
  fn: CCSD
keyword: 3d-ic
keyword: exploration
keyword: infoeu-reposemanticsdoctoralthesis
keyword: mise-en-oeuvre-de-conception-physique
keyword: mpsoc
keyword: noc
keyword: physical-design
keyword: spiotherengineering-sciences-physicsother
keyword: theses
landing page: https://theses.hal.science/tel-00934780

ASIC Design Methodologies for 3D NOC Based 3D Heterogeneous Multiprocessor on Chip
type: Distribution
format: HTML
issued: 2026-05-07T07:31:07.494875
modified: 2026-05-07T07:31:07.474104
access URL: https://theses.hal.science/tel-00934780

test_moissonnage_selune
type: Agent