A machine-learning based methodology to design analytical area and power models of highly parametric networks-on-chip
type: Dataset
description: In the last decade, Networks-on-chip (NoCs) have emerged as an efficient and flexible interconnect solution to handle the increasing number of processing elements included in Systems-on-chip (SoCs). NoCs are able to handle high-bandwidth and scalability needs under tight performance constraints. However, they are usually characterized by a large number of architectural and implementation parameters, resulting in a vast design space. In these conditions, finding a suitable NoC architecture for specific platform needs is a challenging issue. Moreover, most of main design decisions (e.g. topology, routing scheme, quality of service) are usually made at architectural-level during the first steps of the design flow, but measuring the effects of these decisions on the final implementation at such high level of abstraction is complex. Static analysis (i.e. non-simulation-based methods) has emerged to fulfill this need of reliable performance and cost estimation methods available early in the design flow. As the level of abstraction of static analysis is high, it is unrealistic to expect an accurate estimation of the performance or cost of the chip. Fidelity (i.e. characterization of the main tendencies of a metric) is thus the main objective rather than accuracy. This thesis proposes a modeling methodology to design static cost analysis of NoC components. The proposed method is mainly oriented towards generality. In particular, no assumption is made neither on the number of parameters of the components nor on the dependences of the modeled metric on these parameters. We are then able to address components with millions of configurations possibilities (order of 1e+30 configuration possibilities) and to estimate cost of complex NoCs composed of a large number of these components at architectural-level. It is difficult to model that kind of components with experimental analytical models due to the huge number of configuration possibilities. We thus propose a fully-automated m…
identifier: NNT: 2013GRENM026
issued: 2026-05-05T11:33:09.120609
language: fr
modified: 2026-05-05T11:33:09.120614
contact point: Organization
  fn: CCSD
keyword: analyses-statiques
keyword: infoeu-reposemanticsdoctoralthesis
keyword: infoinfo-ohcomputer-science-csother-csoh
keyword: modeling
keyword: modelisation
keyword: network-on-chip
keyword: niveau-systeme
keyword: performance
keyword: performances
keyword: reseaux-sur-puces
keyword: static-analysis
keyword: system-level
keyword: theses
landing page: https://theses.hal.science/tel-00877956

A machine-learning based methodology to design analytical area and power models of highly parametric networks-on-chip
type: Distribution
format: HTML
issued: 2026-05-05T11:33:09.124338
modified: 2026-05-05T11:33:09.105584
access URL: https://theses.hal.science/tel-00877956

test_moissonnage_selune
type: Agent