In the last decade, Networks-on-chip (NoCs) have emerged as an efficient and flexible interconnect solution to handle the increasing number of processing elements included in Systems-on-chip (SoCs). NoCs are able to handle high-bandwidth and scalability needs under tight performance constraints. However, they are usually characterized by a large number of architectural and implementation parameters, resulting in a vast design space. In these conditions, finding a suitable NoC architecture for specific platform needs is a challenging issue. Moreover, most of main design decisions (e.g. topology, routing scheme, quality of service) are usually made at architectural-level during the first steps of the design flow, but measuring the effects of these decisions on the final implementation at such high level of abstraction is complex. Static analysis (i.e. non-simulation-based methods) has emerged to fulfill this need of reliable performance and cost estimation methods available early in the design flow. As the level of abstraction of static analysis is high, it is unrealistic to expect an accurate estimation of the performance or cost of the chip. Fidelity (i.e. characterization of the main tendencies of a metric) is thus the main objective rather than accuracy. This thesis proposes a modeling methodology to design static cost analysis of NoC components. The proposed method is mainly oriented towards generality. In particular, no assumption is made neither on the number of parameters of the components nor on the dependences of the modeled metric on these parameters. We are then able to address components with millions of configurations possibilities (order of 1e+30 configuration possibilities) and to estimate cost of complex NoCs composed of a large number of these components at architectural-level. It is difficult to model that kind of components with experimental analytical models due to the huge number of configuration possibilities. We thus propose a fully-automated modeling flow which can be applied directly to any architecture and technology. The output of the flow is a NoC component cost predictor able to estimate a metric of interest for any configuration of the design space in few seconds. The flow builds fine-grained analytical models on the basis of gate-level results and a machine-learning method. It is then able to design models with a better fidelity than purely-mathematical methods while preserving their main qualities (i.e. low complexity, early availability). Moreover, it is also able to take into account the effects of the technology on the performance. We propose to use an interpolation method based on Kriging theory. By using Kriging methodology, the number of implementation flow runs required in the modeling process is minimized and the main characteristics of the metrics in space are modeled both globally and locally. The method is applied to model logic area of key NoC components. The inclusion of traffic is then addressed and a NoC router leakage and average dynamic power model is designed on this basis.
A machine-learning based methodology to design analytical area and power models of highly parametric networks-on-chip