Multicore architectures and worst-case execution time
type: Dataset
description: Critical tasks in the context of real-time systems submit to both timing and correctness constraints. Whence, the validation of a real-time system rely on the estimation of its tasks’ Worst case execution times. Resource sharing, as it occurs on multicore architectures, hinders the computation of such estimates. The timing behaviour of a task is impacted by its concurrents, whether because of resource access arbitration or concurrent modifications of a resource state. This study focuses on estimating the contribution of the memory hierarchy to tasks’ worst case execution time. Existing analysis methods, defined for instruction caches, are extended to support private and shared data caches, hence allowing for the analysis of rich memory hierarchies. Cache bypass is then used to reduce the pressure laid by concurrent tasks on shared caches levels. We propose different bypass heuristics, based on the capture of cache blocks’ reuse between memory accesses. Our second proposal is the Preti partitioning scheme which allows for the allocation to tasks of a cache space, free from inter-task conflicts. Preti offers the added benefit of providing for average-case performance to non-critical tasks concurrent to real-time ones on hybrid criticality systems.
landing page: https://theses.hal.science/tel-00870971
identifier: NNT: 2013REN1S034
keyword: analyse-statique
keyword: bypass
keyword: cache-partitioning
keyword: hierarchie-memoire
keyword: infoeu-reposemanticsdoctoralthesis
keyword: infoinfo-ohcomputer-science-csother-csoh
keyword: memory-hierarchy
keyword: multi-coeur
keyword: multicore
keyword: partitionnement-de-cache
keyword: pire-temps-dexecution
keyword: real-time-systems
keyword: static-analysis
keyword: systemes-temps-reel
keyword: theses
keyword: worst-case-execution-time
issued: 2026-05-09T10:50:59.459260
modified: 2026-05-09T10:50:59.459265
language: fr
contact point: Organization
  fn: CCSD

test_moissonnage_selune
type: Agent

Multicore architectures and worst-case execution time
type: Distribution
format: HTML
access URL: https://theses.hal.science/tel-00870971
issued: 2026-05-09T10:50:59.461689
modified: 2026-05-09T10:50:59.437261