Development of CMOS pixel sensors for a vertex detector suited to the ILC
The thesis has been a priority as taking ownership of vertical integration technologies used in the industry to realize a multistage development, and to evaluate the contributions on CMOS pixel sensors (CPS). 3D integration technologies (3DIT) provide a way to mitigate this hampering correlation between speed and resolution, since they allow to staple layers of readout circuitry on top of the sensing layer, which results in a drastic increase of the functionalities located in (the shadow of) each pixel. A multi-layer structure allows for a higher spatial resolution because more and more transistors may be integrated vertically in a relatively small pixel. Moreover, bringing the components of the sensor closer to each other translates in a faster readout, owing to the reduction in the average length of the inner connecting wires. Vertical integration also opens up the possibility of combining different technologies best suited to each of the sensor main functionalities (signal sensing, analog and digital signal processing and transmission). It overcomes the limitations in this way from the foundry manufacturing parameters, which do not allow to fully exploit the potential ofCPS with a single CMOS technology. 3D-CPS are thus expected to overcome most of the limitations of standard 2DCPS, and are therefore suspected to over new perspectives for the innermost layer of the ILC vertex detector.