The main objective of this thesis is to realize a numerical implementation of optical methods of image and signal processing. To achieve this end, we opted to use FPGA (Field Programmable Gate Array) and GPU (Graphical Processing Unit) devices. This choice is justified by their high performance in terms of speed. In addition, to improve productivity, we focused on the reuse of predesigned blocks or "Intellectual Properties" IP. While existing commercial IP are optimized, they are often paid and highly dependent on the card. The first contribution is to provide an optimized IP for Fourier transform (FFT) and the cosine transform (DCT) computing. Indeed, the choice of these two transformations is justified by the widespread use of these two transforms (FFT and DCT), particularly in pattern recognition and compression algorithms. The second contribution is to validate the operation of the proposed IP using a bench test. The last contribution is to implement on FPGA and GPU applications for pattern recognition and compression. One of the convincing results obtained in this thesis is to propose an IP for FFT computing three times faster than Xilinx IP and thus to achieve 4700 correlations per second.
Contribution to the definition, optimization and implementation of signal processing IPs on programmable target