test_moissonnage_selune
type: Agent

Characterization and modelling of 3D inteconnects HF performance for new generation of 3D imagers.
type: Distribution
access URL: https://theses.hal.science/tel-00819827
format: HTML
issued: 2026-05-11T06:03:11.446059
modified: 2026-05-11T06:03:11.410689

Characterization and modelling of 3D inteconnects HF performance for new generation of 3D imagers.
type: Dataset
contact point: Organization
  fn: CCSD
keyword: rf-characterisation
keyword: copper-pillar
keyword: modele-rlcg
keyword: courants-de-foucault
keyword: theses
keyword: spiotherengineering-sciences-physicsother
keyword: infoeu-reposemanticsdoctoralthesis
keyword: integration-3d
keyword: de-embedding
keyword: 3d-ic
keyword: caracterisation-rf
keyword: tsv
keyword: rlcg-model
keyword: eddy-current
landing page: https://theses.hal.science/tel-00819827
description: The aim of this doctoral work is to study the new kind of interconnections like TSV (Through Silicon Via), redistribution lines (RDL) and copper pillars used in 3D integration context in advanced microelectronic components. An example of 3D integration application could be an imager designed by staking an optical sensor chip upon a processor chip. In order to understand and quantify the electrical behaviour of these new interconnection components, the first issue was about electrical characterization in a very wide frequency band (10 MHz - 60 GHz) of these elements, buried in their complex environment, in particular with the analysis of the silicon substrate loss impact which can be found in a wide band of conductivities from very low (0 S/m) to very high (10 000 S/m). Subsequently, a second issue appears from the need to develop mathematical models to predict the electrical behavior of 3D interconnects. The developed models have to take into account losses, coupling effects and some phenomena appearing with the rise of frequency (eddy currents) according to material characteristics, dimensions and architecture (from high to low density of integration). Finally, based on developed models, the last part presents a study on routing strategies in the 3D stacking chip from the analysis of signal integrity. By contrasting various environments, binary signals flow or dimensions of TSV and RDL, conclusions emerge on the best strategies to use to improve performances of circuits designed in 3D integration.
identifier: NNT: 2012GRENT071
issued: 2026-05-11T06:03:11.429575
language: fr
modified: 2026-05-11T06:03:11.429579