This work deals with the development of vertical thin film transistors (VTFTs) via the fabrication processes and the analysis of the electrical characteristics. The low-temperature (T ≤ 600°C) polycrystalline silicon technology is adopted in the fabrication processes. The first step of the work consists in the fabrication and characterization of VTFTs obtained by rotating the lateral thin film transistors (LTFTs) 90°. The feasibility of VTFTs fabrication is validated with an ION/IOFF ratio of about 10³, and it is analyzed that the large overlapping area between source and drain leads to a large off-current IOFF. The second step of the work lies in the partial suppression of the large overlapping area, and therefore, an ION/IOFF ratio of almost 10⁵ is obtained. The third step of the work deals with the proposal of a new VTFT structure that absolutely eliminates the overlapping area. Different improvements have been made on this new VTFT structure, especially by optimization of the following parameters: the active layer thickness, type and thickness of the barrier layer, and the geometric dimension. The optimized transistor highlights an ION/IOFF ratio of higher than 10⁵ with a reduced off-current IOFF, high stability and good reproducibility. P and N-type VTFTs have also been fabricated and showed symmetrical electrical characteristics; they are thus suitable for CMOS-like VTFT applications.
Development and fabrication of vertical thin film transistors based on low temperature polycrystalline silicon technology