Exploration and optimization of tree-based FPGA architectures
Today, FPGAs (Field Programmable Gate Arrays) become important actors in the computational devices domain that was originally dominated by microprocessors and ASICs. FPGA design big challenge is to nd a good tradeoff between exibility and performances. Three factors combine to determine the characteristics of an FPGA: quality of its architecture, quality of the CAD tools used to map circuits into the FPGA, and its electrical design. The subject of this dissertation is the exploration of new interconnect topologies and architectures that may play important roles in FPGA performances improvement. In fact interconnect is the dominant factor in terms of area (90%) and power dissipation (60%). The main architectures under exploration have Tree-based or Mesh- Based topology. The main results are the following: We rst explore different Tree-based architectures and we compare them to Meshbased architecture in terms of area. For this purpose we develop an exploration tools platform allowing to implement various benchmark circuits on the target architecture. Using experimental evaluation, we de ne a new Tree-based FPGA architecture and we show that it has good performances and density characteristics.We show, based on total cells area evaluation, that using the proposed topology we achieve a gain of 56% compared to the common Mesh-based FPGA architecture. This is due essentially to the high interconnect utilization achieved by this architecture. We explore the effect of different architecture parameters: Rent's ratio, cluster sizes, and LUTs sizes.We show how they interact and the way to tune them to satisfy different speci c applicative constraints (density, performance and power). Finally, we propose an architecture that takes advantage of both Mesh and Tree strongest points. We unify both structures by building clusters with a Tree-based local interconnect and we connect these clusters by a Mesh-based interconnect.We show that the resulting architecture presents a good tradeoff between layout scalability and area density.