test_moissonnage_selune
type: Agent

Towards Optimized Flexible Multi-ASIP Architectures for LDPC/Turbo Decoding
type: Dataset
contact point: Organization
  fn: CCSD
keyword: spitronengineering-sciences-physicselectronics
keyword: asip
keyword: flexibilite
keyword: theses
keyword: turbo-codes
keyword: flexibility
keyword: efficacite-architecturale
keyword: architecture-efficiency
keyword: infoeu-reposemanticsdoctoralthesis
keyword: multiprocesseur
keyword: fpga-prototyping
keyword: turbocodes
keyword: lte
keyword: wimax
keyword: ldpc-codes
keyword: codes-ldpc
keyword: channel-decoding
keyword: wifi
keyword: decodage-de-canal
keyword: multiprocessor
keyword: prototypage-fpga
landing page: https://theses.hal.science/tel-00811941
description: Large variety of channel coding techniques are specified in existing and emerging digital communication standards, each suitable for specific application needs (frame size, transmission channel, signal-to-noise ratio, bandwidth, etc). Considering the emerging multi-mode and multi-standard applications, as well as the increasing interest for Software Defined Radio (SDR) and Cognitive Radio (CR) applications, flexible implementations combining multiple error correction techniques becomes mandatory. However, the need of optimal solutions in terms of performance, area, and power consumption is increasing too and cannot be neglected against flexibility. In this context, this thesis work has investigated multi-ASIP architecture model towards the target of unifying flexibility-oriented and optimization-oriented approaches in the design of flexible channel decoders. By considering mainly the challenging Turbo and LDPC decoding applications, multi-ASIP channel decoder architectures are proposed targeting high flexibility combined with high architecture efficiency in terms of bits/cycle/iteration/mm2. Different architecture alternatives and design approaches are explored. Three original contributions have been proposed. The first one concerns the design of a scalable and flexible high throughput multi-ASIP LDPC/Turbo decoder. Several design objectives have been attained in this work in terms of scalability, resource sharing, and configurability speed. The proposed DecASIP supports the decoding of LDPC and Turbo codes specified in WiFi, WiMAX, and LTE standards. The achieved scalability through the multi-ASIP NoC based approach enables the accommodation of current and future high throughput requirements. The second contribution concerns the design of a parameterized ASIP for Turbo decoding (TDecASIP). Here the objective was to investigate the maximum attainable architecture efficiency for ASIP-based Turbo decoding when maximizing the usage of sub-block parallelism. Furthermore…
issued: 2026-05-11T13:22:10.890443
language: en
modified: 2026-05-11T13:22:10.890447

Towards Optimized Flexible Multi-ASIP Architectures for LDPC/Turbo Decoding
type: Distribution
access URL: https://theses.hal.science/tel-00811941
format: HTML
issued: 2026-05-11T13:22:10.944648
modified: 2026-05-11T13:22:10.849826