Bipartite edge coloring approach for designing parallel hardware interleaver architecture
type: Dataset
description: Nowadays, Turbo and LDPC codes are two families of codes that are extensively used in current communication standards due to their excellent error correction capabilities. However, hardware design of coders and decoders for high data rate applications is not a straightforward process. For high data rates, decoders are implemented on parallel architectures in which more than one processing elements decode the received data. To achieve high memory bandwidth, the main memory is divided into smaller memory banks so that multiple data values can be fetched from or stored to memory concurrently. However, due to scrambling caused by interleaving law, this parallelization results in communication or memory access conflicts which occur when multiple data values are fetched from or stored in the same memory bank at the same time. This problem is called Memory conflict Problem. It increases latency of memory accesses due to the presence of conflict management mechanisms in communication network and unfortunately decreases system throughput while augmenting system cost. To tackle the memory conflict problems, three different types of approaches are used in literature. In first type of approaches, different algorithms to construct conflict free interleaving law are proposed. The main reason to develop these techniques is to construct "architecture friendly" codes with good error correction capabilities in order to reduce hardware cost. However, architectural constraints applied during code design may impede error correction performance of the codes. In a second type of approaches, different design innovations are introduced to tackle memory conflict problem. Flexible and scalable interconnection network with sufficient path diversity and additional storing elements are introduced to handle memory conflicts. However, flexible networks require large silicon area and cost. In addition, delay introduced due to conflict management mechanisms degrades the maximum throughput and makes …
issued: 2026-05-14T06:53:24.355312
language: en
modified: 2026-05-14T06:53:24.355317
contact point: Organization
  fn: CCSD
keyword: infoeu-reposemanticsdoctoralthesis
keyword: infoinfo-arcomputer-science-cshardware-architecture-csar
keyword: infoinfo-tscomputer-science-cssignal-and-image-processing
keyword: interleaver
keyword: placement-memoire
keyword: spisignalengineering-sciences-physicssignal-and-image-processing
keyword: theses
keyword: traitement-du-signal
landing page: https://theses.hal.science/tel-00790045

Bipartite edge coloring approach for designing parallel hardware interleaver architecture
type: Distribution
format: HTML
issued: 2026-05-14T06:53:24.377643
modified: 2026-05-14T06:53:24.336670
access URL: https://theses.hal.science/tel-00790045

test_moissonnage_selune
type: Agent