Low power reconfigurable memory hierarchy for embedded system
The continuous improvement of digital microelectronics technologies has permitted to embed digital circuits into many different objects (e.g cell phones, GPS, cars, etc.). As a consequence, their functionality as well as their performances have been significantly enhanced at a low cost. Meanwhile, the fast and steady growth of the embedded application has brought unprecedented constraints, such as high performance and low power consumption requirements. In this context, the emergence of the coarse-grained reconfigurable architectures has led to promising trade-offs between performances and flexibility. Up to date, the hardware reconfiguration paradigm implementation has mainly affected the processing unit structure. However, embedded multimedia applications compute growing sets of data which results in a lot of memory accesses. In addition, the diversity and evolution of embedded processing do not allow to build dedicated storage unit in order to respect high performance and low power consumption requirements. So, we developped the RTL model, verified functionally and validated, of a reconfigurable architecture which has been named MOREA (acronym of Memory-Oriented Reconfigurable Embedded Architecture). MOREA is organised as an array of processing and storage tiles which can run various processes of an application. In a tile, the tasks of a process are computed by four clusters which integrate memory and computing ressources. These clusters communicate with a global memory bank, which stores the data shared by the tasks of the process, thanks to a programmable crossbar interconnection. Consequently, this structure allows to minimize data transfers within MOREA and especially the number of memory accesses and therefore, allows to reduce their impact on the computing power and energy dissipation of the system. Moreover, the resulting gains are maximized thanks to a programmable address generation unit whose architecture has been defined according to the characteristics of the digital signal and image processing applications. This unit is built from an hardware accelerator which is responsible of the generation of regular address sequences. As a result, this architecture improves significantly the performances of the address generation unit by a factor 6 in terms of Millions of Addresses generated Per Second (MAPS) while reducing drastically its power consumption by a gain of 96%, as compared with a classic programmable solution.