test_moissonnage_selune
type: Agent

Low power reconfigurable memory hierarchy for embedded system
type: Distribution
access URL: https://theses.hal.science/tel-00783898
format: HTML
issued: 2026-05-14T18:13:59.014167
modified: 2026-05-14T18:13:58.971051

Low power reconfigurable memory hierarchy for embedded system
type: Dataset
contact point: Organization
  fn: CCSD
keyword: traitement-du-signal-et-de-limage
keyword: infoeu-reposemanticsdoctoralthesis
keyword: signal-and-image-processing
keyword: hardware-reconfiguration
keyword: energy-efficiency
keyword: embedded-applications
keyword: applications-embarquees
keyword: memory-hierarchy
keyword: hierarchie-memoire
keyword: soc
keyword: generation-dadresses
keyword: efficacite-energetique
keyword: spitronengineering-sciences-physicselectronics
keyword: address-generation
keyword: reconfiguration-materielle
keyword: theses
keyword: multimedia
landing page: https://theses.hal.science/tel-00783898
description: The continuous improvement of digital microelectronics technologies has permitted to embed digital circuits into many different objects (e.g cell phones, GPS, cars, etc.). As a consequence, their functionality as well as their performances have been significantly enhanced at a low cost. Meanwhile, the fast and steady growth of the embedded application has brought unprecedented constraints, such as high performance and low power consumption requirements. In this context, the emergence of the coarse-grained reconfigurable architectures has led to promising trade-offs between performances and flexibility. Up to date, the hardware reconfiguration paradigm implementation has mainly affected the processing unit structure. However, embedded multimedia applications compute growing sets of data which results in a lot of memory accesses. In addition, the diversity and evolution of embedded processing do not allow to build dedicated storage unit in order to respect high performance and low power consumption requirements. So, we developped the RTL model, verified functionally and validated, of a reconfigurable architecture which has been named MOREA (acronym of Memory-Oriented Reconfigurable Embedded Architecture). MOREA is organised as an array of processing and storage tiles which can run various processes of an application. In a tile, the tasks of a process are computed by four clusters which integrate memory and computing ressources. These clusters communicate with a global memory bank, which stores the data shared by the tasks of the process, thanks to a programmable crossbar interconnection. Consequently, this structure allows to minimize data transfers within MOREA and especially the number of memory accesses and therefore, allows to reduce their impact on the computing power and energy dissipation of the system. Moreover, the resulting gains are maximized thanks to a programmable address generation unit whose architecture has been defined according to the characteristic…
issued: 2026-05-14T18:13:59.005126
language: fr
modified: 2026-05-14T18:13:59.005131