Decoupled approaches to register and software controlled memory allocations
type: Dataset
description: Despite the benefit of the memory hierarchy, it is still essential, in order to reduce accesses to higher levels of memory, to have an efficient usage of registers and local memories (also called scratchpad memories) present in most embedded processors, graphical processors (GPUs) and network processors. During the compilation, from a source language to an executable code, there are two optimizations that are of utmost importance: the register allocation and the local memory allocation. In this thesis's report we are interested in decoupled approaches, solving separately the allocation and assignment problems, that helps to improve the quality of the register and local memory allocations. In the first part of this thesis we are interested in two aspects of the register allocation problem: the improvements of the just-in-time (JIT) register allocation and the spill minimization problem. We introduce the split register allocation which leverages the decoupled approach to improve register allocation in the context of JIT compilation. We experimentally validate the effectiveness of split register allocation and its portability with respect to register count variations, relying on annotations whose impact on the bytecode size is negligible. We introduce a new decoupled approach, called iterated-optimal allocation, which focus on the spill minimization problem. The iterated-optimal allocation algorithm achieves results close to optimal while offering pseudo-polynomial guarantees for SSA programs and fast allocations on general programs. In the second part of this thesis, we study how a decoupled local memory allocation can be proposed in light of recent progresses in register allocation. We first validate our intuition for decoupled approach to local memory allocation. Then, we study the local memory allocation in a more theoretical way setting the junction between local memory allocation for linearized programs and weighted interval graph coloring. We design and analyze …
identifier: NNT: 2011PA112349
issued: 2026-05-29T03:06:08.645888
language: en
modified: 2026-05-29T03:06:08.645903
contact point: Organization
  fn: CCSD
keyword: allocation-de-memoire
keyword: allocation-de-registres
keyword: coloration-de-graphes-ponderes
keyword: compilation
keyword: infoeu-reposemanticsdoctoralthesis
keyword: infoinfo-ohcomputer-science-csother-csoh
keyword: memory-allocations
keyword: probleme-de-submarine-building
keyword: register-allocation
keyword: scratchpad
keyword: submarine-building-problem
keyword: theses
keyword: weighted-graphs-coloring
landing page: https://theses.hal.science/tel-00769403

Decoupled approaches to register and software controlled memory allocations
type: Distribution
format: HTML
issued: 2026-05-29T03:06:08.752915
modified: 2026-05-29T03:06:08.584357
access URL: https://theses.hal.science/tel-00769403

test_moissonnage_selune
type: Agent