@prefix dcat: <http://www.w3.org/ns/dcat#> .
@prefix dct: <http://purl.org/dc/terms/> .
@prefix foaf: <http://xmlns.com/foaf/0.1/> .
@prefix vcard: <http://www.w3.org/2006/vcard/ns#> .
@prefix xsd: <http://www.w3.org/2001/XMLSchema#> .

<https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00998915v1> a dcat:Dataset ;
    dct:description """
              Register allocation is a much studied problem. A particularly important context for optimizing register allocation is within loops, since a significant fraction of the execution time of programs is often inside loop code. A variety of algorithms have been proposed in the past for register allocation, but the complexity of the problem has resulted in a decoupling of several important aspects, including loop unrolling, register promotion, and instruction reordering. In this paper, we develop an approach to register allocation and promotion in a unified optimization framework that simultaneously considers the impact of loop unrolling and instruction scheduling. This is done via a novel instruction tiling approach where instructions within a loop are represented along one dimension and innermost loop iterations along the other dimension. By exploiting the regularity along the loop dimension, and imposing essential dependence based constraints on intra-tile execution order, the problem of optimizing register pressure is cast in a constraint programming formalism. Experimental results are provided from thousands of innermost loops extracted from the SPEC benchmarks, demonstrating improvements over the current state-of-the-art.
            """ ;
    dct:identifier "Report N°: RR-8541" ;
    dct:issued "2026-05-05T09:51:21.598856"^^xsd:dateTime ;
    dct:language "en" ;
    dct:modified "2026-05-05T09:51:21.598861"^^xsd:dateTime ;
    dct:publisher <https://rec.harvest-normandie.data4citizen.com/organization/cce9db95-46d9-4dc2-84b6-764215d0a002> ;
    dct:title "A Tiling Perspective for Register Optimization" ;
    dcat:contactPoint [ a vcard:Organization ;
            vcard:fn "CCSD" ] ;
    dcat:distribution <https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00998915v1/resource/ff9a8dee-6260-42dd-8488-80ba408ef077> ;
    dcat:keyword "acm-d-softwared3-programming-languagesd34-processorsd340-code-generation",
        "acm-d-softwared3-programming-languagesd34-processorsd341-compilers",
        "acm-d-softwared3-programming-languagesd34-processorsd346-optimization",
        "compilation",
        "compiler-optimisation",
        "constraint-programming",
        "infoeu-reposemanticsreport",
        "infoinfo-dscomputer-science-csdata-structures-and-algorithms-csds",
        "infoinfo-locomputer-science-cslogic-in-computer-science-cslo",
        "infoinfo-plcomputer-science-csprogramming-languages-cspl",
        "infoinfo-rocomputer-science-csoperations-research-mathoc",
        "locality",
        "loop-transformations",
        "loop-unrolling",
        "register-allocation",
        "register-promotion",
        "register-spilling",
        "register-tiling",
        "reports",
        "scheduling",
        "tiling" ;
    dcat:landingPage <https://inria.hal.science/hal-00998915> .

<https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00998915v1/resource/ff9a8dee-6260-42dd-8488-80ba408ef077> a dcat:Distribution ;
    dct:format "HTML" ;
    dct:issued "2026-05-05T09:51:21.610106"^^xsd:dateTime ;
    dct:modified "2026-05-05T09:51:21.575677"^^xsd:dateTime ;
    dct:title "A Tiling Perspective for Register Optimization" ;
    dcat:accessURL <https://inria.hal.science/hal-00998915> .

<https://rec.harvest-normandie.data4citizen.com/organization/cce9db95-46d9-4dc2-84b6-764215d0a002> a foaf:Agent ;
    foaf:name "test_moissonnage_selune" .

<https://inria.hal.science/hal-00998915> a foaf:Document .