@prefix dcat: <http://www.w3.org/ns/dcat#> .
@prefix dct: <http://purl.org/dc/terms/> .
@prefix foaf: <http://xmlns.com/foaf/0.1/> .
@prefix vcard: <http://www.w3.org/2006/vcard/ns#> .
@prefix xsd: <http://www.w3.org/2001/XMLSchema#> .

<https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00856160v1> a dcat:Dataset ;
    dct:description """
              ARM ISA-based processors are no longer low-cost low-power processors. Nowadays ARM ISA based processor manufacturers are struggling to implement medium-end to high-end processor cores, and this implies implementing a state-of-the-art out-of-order execution engine. Unfortunately providing efficient out-of-order execution on legacy ARM codes may be quite challenging due to predicated instructions. In this paper, we propose a new hardware solution, Selective Prediction and REplay for Predicated Instructions (SPREPI), to provide efficient out-of-order execution of codes featuring predicated instructions. Predicting the predicated instructions addresses the so-called multiple definition problem. Predicated instructions are predicted using either a global branch-and-predicate history predictor or a global history predictor. But systematic usage of predicate prediction sometimes impairs the performance dramatically. Efficient filters are proposed to disable predicate prediction uses when they are likely to be counter-productive. Moreover predicate misprediction penalty can be as high as the branch mispenalty. To reduce this penalty we introduce a specific selective replay hardware component targeting mispredicted predicated instructions. SPREPI is shown to allow high out-order execution performance on ARM codes generated even with a compiler applying if-conversion only to very short branches. Moreover since SPREPI predicts most of the predicated instructions, a relatively inefficient hardware solution is sufficient for executing the few predicated instructions on which prediction is not used.
            """ ;
    dct:identifier "Report N°: RR-8351" ;
    dct:issued "2026-05-09T23:01:12.061408"^^xsd:dateTime ;
    dct:language "en" ;
    dct:modified "2026-05-09T23:01:12.061413"^^xsd:dateTime ;
    dct:publisher <https://rec.harvest-normandie.data4citizen.com/organization/cce9db95-46d9-4dc2-84b6-764215d0a002> ;
    dct:title "SPREPI: Selective Prediction and REplay for predicated Instructions" ;
    dcat:contactPoint [ a vcard:Organization ;
            vcard:fn "CCSD" ] ;
    dcat:distribution <https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00856160v1/resource/1db3129b-fe08-45cf-b92c-20715ec74854> ;
    dcat:keyword "arm",
        "infoeu-reposemanticsreport",
        "infoinfo-arcomputer-science-cshardware-architecture-csar",
        "out-of-order-execution",
        "predicated-instructions",
        "predication",
        "prediction",
        "replay",
        "reports",
        "seletive" ;
    dcat:landingPage <https://inria.hal.science/hal-00856160> .

<https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00856160v1/resource/1db3129b-fe08-45cf-b92c-20715ec74854> a dcat:Distribution ;
    dct:format "HTML" ;
    dct:issued "2026-05-09T23:01:12.072060"^^xsd:dateTime ;
    dct:modified "2026-05-09T23:01:12.046642"^^xsd:dateTime ;
    dct:title "SPREPI: Selective Prediction and REplay for predicated Instructions" ;
    dcat:accessURL <https://inria.hal.science/hal-00856160> .

<https://rec.harvest-normandie.data4citizen.com/organization/cce9db95-46d9-4dc2-84b6-764215d0a002> a foaf:Agent ;
    foaf:name "test_moissonnage_selune" .

<https://inria.hal.science/hal-00856160> a foaf:Document .