Designing Robust Single-Chip Massively-Parallel Tera-Device Processors
type: Dataset
description: International audience
issued: 2026-05-11T09:35:48.495381
language: en
modified: 2026-05-11T09:35:48.495385
contact point: Organization
  fn: CCSD
keyword: conference-papers
keyword: infoeu-reposemanticsconferenceobject
keyword: pacs-8542
keyword: processors
keyword: single-chip
keyword: spinanoengineering-sciences-physicsmicro-and-nanotechnologiesmicroelectronics
landing page: Proc of 4th Design for Reliability Workshop (DFR)

Designing Robust Single-Chip Massively-Parallel Tera-Device Processors
type: Distribution
format: HTML
issued: 2026-05-11T09:35:48.503953
modified: 2026-05-11T09:35:48.485412
access URL: https://hal.science/hal-00815969

test_moissonnage_selune
type: Agent