This paper presents an abstract clock-based reasoning for the rapid prototyping of embedded applications executed on multiprocessor systems-on-chip (MPSoCs). In this framework, a synchronous multi-clock modeling of application behaviors is considered. The scheduling of these applications on execution platforms composed of processors operating at various frequencies is described and analyzed with the proposed clock modeling. As in the static scheduling of synchronous dataflows (SDFs), requirements for admissible schedules are investigated, which come not only from expected application behavior, but also from execution platform properties. An algorithm is proposed to construct admissible schedules respecting the identified requirements. It is then adapted to support the synthesis of admissible schedules for adaptive system behaviors including, e.g., dynamic frequency changing or task migration. The modeling, analysis and algorithms presented in this paper have been implemented in a prototype tool named CLASSY (standing for CLock AnalySis SYstem), providing also a way to visualize design results. The proposed approach provides a fast and cost-effective means to define correct-by-construction systems and simplify the design space exploration of complex embedded systems.
CLASSY: a Clock Analysis System for Rapid Prototyping of Embedded Applications on MPSoCs