@prefix dcat: <http://www.w3.org/ns/dcat#> .
@prefix dct: <http://purl.org/dc/terms/> .
@prefix foaf: <http://xmlns.com/foaf/0.1/> .
@prefix vcard: <http://www.w3.org/2006/vcard/ns#> .
@prefix xsd: <http://www.w3.org/2001/XMLSchema#> .

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    dct:description """
              Wavelet transform coding has been drawing much attention because of its ability to decompose images into a hierarchical structure that is suitable for adaptive processing in the transform domain. This paper presents an efficient VLSI design of one-dimensional direct discrete wavelet transform processor. The proposed architecture computes three DWT stages and uses four parallel filters. The architecture is simple and offers 16-bit precision on input and output data. It consists of three basic units: one storage unit, four filters, and a control unit. No memory or registers are used for storing intermediate results. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches. The architecture can compute DWT at a data rate of 7x10/sup 6/ samples/s corresponding to a typical clock speed of 7 MHz. The architecture is simulated and verified at the gate level in VLSI. Process parameters used were those of 0.6 mu m technology. The chip area is about 15.7 mm/sup 2/
            """ ;
    dct:identifier "hal-00081537" ;
    dct:issued "2026-05-11T10:09:00.270298"^^xsd:dateTime ;
    dct:language "en" ;
    dct:modified "2026-05-11T10:09:00.270303"^^xsd:dateTime ;
    dct:publisher <https://rec.harvest-normandie.data4citizen.com/organization/cce9db95-46d9-4dc2-84b6-764215d0a002> ;
    dct:title "VLSI design of 1-D DWT architecture with parallel filters" ;
    dcat:contactPoint [ a vcard:Organization ;
            vcard:fn "CCSD" ] ;
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    dcat:keyword "adaptive-signal-processing",
        "digital-signal-processing-chips",
        "discrete-wavelet-transforms",
        "infoeu-reposemanticsarticle",
        "journal-articles",
        "pacs-8542",
        "parallel-architectures",
        "spinanoengineering-sciences-physicsmicro-and-nanotechnologiesmicroelectronics",
        "vlsi-" ;
    dcat:landingPage <ISSN:%200167-9260> .

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    dct:format "HTML" ;
    dct:issued "2026-05-11T10:09:00.288841"^^xsd:dateTime ;
    dct:modified "2026-05-11T10:09:00.257173"^^xsd:dateTime ;
    dct:title "VLSI design of 1-D DWT architecture with parallel filters" ;
    dcat:accessURL <https://hal.science/hal-00081537> .

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