A complete methodology to estimate power consumption at the C-level for on-the-shelf processors is proposed. It relies on the Functional-Level Power Analysis, which results in a power model of the processor; this model describes the consumption variations relatively to algorithmic and configuration parameters. Some parameters can be predicted directly from the C-algorithm with simple assumptions on the compilation. Estimation results are summarized on a consumption map; then the designer can check the algorithm with the application constraints. Maximum and minimum bounds are also provided. Applied to the TI C6x, the estimation method provides a maximum error of 6% against measurements for classical DSP algorithms.
Power Consumption Estimation of a C-algorithm: A New Perspective for Software Design