@prefix dcat: <http://www.w3.org/ns/dcat#> .
@prefix dct: <http://purl.org/dc/terms/> .
@prefix foaf: <http://xmlns.com/foaf/0.1/> .
@prefix vcard: <http://www.w3.org/2006/vcard/ns#> .
@prefix xsd: <http://www.w3.org/2001/XMLSchema#> .

<https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00077297v1> a dcat:Dataset ;
    dct:description """
              The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.
            """ ;
    dct:identifier "hal-00077297" ;
    dct:issued "2026-05-15T09:50:53.069831"^^xsd:dateTime ;
    dct:language "en" ;
    dct:modified "2026-05-15T09:50:53.069836"^^xsd:dateTime ;
    dct:publisher <https://rec.harvest-normandie.data4citizen.com/organization/cce9db95-46d9-4dc2-84b6-764215d0a002> ;
    dct:title "High-level synthesis under I/O Timing and Memory constraints" ;
    dcat:contactPoint [ a vcard:Organization ;
            vcard:fn "CCSD" ] ;
    dcat:distribution <https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00077297v1/resource/63da3047-70ad-4fef-a609-fdb21d6ee8ac> ;
    dcat:keyword "conference-papers",
        "high-level-synthesis",
        "infoeu-reposemanticsconferenceobject",
        "infoinfo-arcomputer-science-cshardware-architecture-csar",
        "io-and-memory-constraint",
        "spinanoengineering-sciences-physicsmicro-and-nanotechnologiesmicroelectronics" ;
    dcat:landingPage <International%20Symposium%20on%20Circuits%20And%20Systems> .

<International%20Symposium%20on%20Circuits%20And%20Systems> a foaf:Document .

<https://rec.harvest-normandie.data4citizen.com/dataset/oai-hal-hal-00077297v1/resource/63da3047-70ad-4fef-a609-fdb21d6ee8ac> a dcat:Distribution ;
    dct:format "HTML" ;
    dct:issued "2026-05-15T09:50:53.072786"^^xsd:dateTime ;
    dct:modified "2026-05-15T09:50:53.056038"^^xsd:dateTime ;
    dct:title "High-level synthesis under I/O Timing and Memory constraints" ;
    dcat:accessURL <https://hal.science/hal-00077297> .

<https://rec.harvest-normandie.data4citizen.com/organization/cce9db95-46d9-4dc2-84b6-764215d0a002> a foaf:Agent ;
    foaf:name "test_moissonnage_selune" .